In the manufacture of semiconductor memory devices, process margins for lithography are decreased as the degree of device integration is increased. Specifically, when misalignment occurs, that is, layers of a semiconductor device are not effectively aligned in lithography, the resulting semiconductor device may be defective and yield may be reduced.
When contacts fail to efficiently connect the source/drain of a transistor with metal wires due to misalignment, leakage current increases sharply. Besides the increase in leakage current due to this abnormal process condition, diode leakage current due to an inadequate implant process condition in a PN junction diode region formed between a source/drain region and a well region also considerably affects the characteristics of the device.
Specifically, to make a more competitive device, a flash memory device should retain written data for a long time, while increasing the degree of integration in cell regions. From this point of view, the manufacture of a flash memory device below 90 nm requires the capability of rapidly and accurately detecting even a small change in a process. In the case of flash memory devices below 90 nm, when contacts land on an active area, high precision is required. If a margin for overlay misalignment in a process is not sufficient, increased leakage current inevitably occurs, causing fatal errors to data retention in a flash memory device. The deterioration of data retention performance also results from leakage current of the aforementioned PN junction diode formed between the source/drain and a well.
To monitor for errors in manufacturing processes of semiconductor devices, a test element group for monitoring may be provided in a scribe line between dies. The test element group includes a pattern for measuring leakage current at a PN junction. Such a pattern may have a structure which includes a plurality of contacts formed in a wide active area, in which a well and a PN junction are formed.
FIG. 1A is a top view illustrating a test element group for monitoring used to measure leakage current, and FIG. 1B is a cross-sectional view taken along line 1-1′ of FIG. 1A. As shown in FIG. 1B, a test element group for monitoring includes device isolation layers 12 formed in a semiconductor substrate 11. A PN junction 13 including a well and an impurity layer may be formed by an ion injection process in an active area separated by the device isolation layers 12. A titanium or cobalt silicide layer 14 may be formed over the PN junction 13 to reduce contact resistance. The silicide layer 14 is connected to a first metal layer 17 through contacts 16 formed subsequently thereto. A pre-metal dielectric (PMD) layer 15 acts as an insulating layer which fills an area between the first metal layer 17 and the active area.
By using the test element group for monitoring with the above structure, leakage current generated at the PN junction 13 due to abnormality of process conditions, can be monitored. Abnormalities in the amount of impurities injected in the ion injection process, an ion injection energy and a thickness of the silicide layer 14 may be monitored. The leakage current can be calculated by applying a certain voltage to the first metal layer 17 and a second metal layer, which is connected to well pickup contacts formed in the well of the PN junction 13, and measuring current flowing through the PN junction 13. For example, anode (positive) voltage may be applied to the first metal layer 17 where the junction is an N+-type active area and a P-type well, and cathode (negative) voltage is applied to the first metal layer 17 where the junction is a P+-type active area and an N-type well. However, in the pattern having the above structure, even when misalignment occurs between the contacts 16 and the active area in lithography, a contact area between the contacts 16 and the active area is not changed. Therefore, the leakage current is not increased sharply.
To determine whether the leakage current is generated by misalignment of the contacts 16 and to detect the leakage current due to the misalignment of the contacts 16, a new test element group suitable to accomplish such purposes is required. Up to now, there has not been a test element group capable of effectively monitoring the leakage current due to overlay misalignment of the contacts 16 on the active area, and accurately monitoring the leakage current features in the PN junction diode region formed between the source/drain and the well.